Each IC of a particular device can be made up of billions of interconnected devices, such as transistors, resistors, capacitors, and diodes, located on one or more layers of an IC. The quality and viability of a product including an IC can be at least partially dependent on the techniques used for fabricating the IC and the structure of various components therein. Fabrication of an IC can include two major phases: front end of line (FEOL) processes and back end of line (BEOL) processes. FEOL processes generally include fabrication processes performed on a wafer up to and including the formation of a first “metal level,” i.e., a metal wire for connecting several semiconductor devices together. BEOL processes generally include steps subsequent to forming a first metal level, including the formation of all subsequent metal levels. To provide greater scaling and sophistication of the fabricated device, the number of metal levels can be varied to suit a particular application, e.g., by providing four to six metal levels, or as many as, in a further example, sixteen or more metal levels. To connect components formed in FEOL processes to those formed in BEOL processes, a local interconnect (LI) layer can be formed on components fabricated in the FEOL processes, followed by deposition and/or bonding of components fabricated in BEOL processes onto the LI layer.
Components fabricated in FEOL processes can be electrically interconnected to those formed in BEOL processes by the use of vertical metal wires, also known as “vias.” Each via can traverse one or more regions of dielectric material, in addition to other intervening metal levels and/or insulator layers of dielectric material. Vias can present a significant manufacturing challenge, because an electrical short affecting the via can affect the operation of an entire product. In some circumstances, the amount of electrical resistance across a via may vary based on the processes used to fabricate the via and/or its adjacent components or layers. Process improvement in the fabrication of IC products thus may be concerned with reducing the number of potential defects in an LI layer and elsewhere, while maintaining process simplicity and reducing the total number of steps required to fabricate an IC.